1. Field of the Invention
The present invention relates to the process of computing (or estimating) capacitance in an electrical structure. More specifically, the present invention relates to the process of estimating equivalent capacitance using statistical techniques.
2. Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can be largely attributed to the incredible-miniaturization of integrated circuits. Today, integrated circuits are being built at deep sub-micron (DSM) dimensions. At these dimensions, accurate extraction (or computation) of equivalent capacitances between signal (or interconnect) nets has become absolutely critical for performing any subsequent timing or signal integrity analyses.
Present capacitance extraction techniques include Finite Element Method (FEM), Boundary Element Method (BEM), and methods based on Monte Carlo Integration.
Note that modern fabrication technologies can have more than 10 routing layers that have non-uniform metal densities. This can result in large variations in the wafer topography which can cause severe manufacturing problems. Hence, Chemical-Mechanical Polishing (CMP) is typically used to reduce topography variation of these layers. Unfortunately, non-uniform metal densities can result in “dishing” during CMP, which can lead to severe manufacturing problems. Hence, to improve manufacturability, foundries often use fill nets (also known as dummy fills or fill metals) in low density regions to make the metal densities more uniform.
FIG. 1 illustrates a portion of an integrated circuit in which fill nets 102 are situated between two signal nets, 104 and 106, in accordance with an embodiment of the present invention. (Note that the dielectric material between these nets has not been illustrated in FIG. 1 for the sake of clarity.)
Note that for timing and signal integrity analyses, circuit designers are usually interested in the equivalent capacitance between signal nets, such as equivalent capacitance 108, which accounts for the presence of floating fill nets. On the other hand, the direct (or coupling) capacitance between a signal net and a floating fill net (or between two fill nets), such as direct (or coupling) capacitance 110, is typically not useful for timing and signal integrity analyses. Moreover, since floating fill nets can substantially increase the equivalent capacitance between signal nets, their effect on the equivalent capacitance cannot be ignored.
Unfortunately, modern integrated circuits often have a large number of floating fill nets in the proximity of a signal net. This can cause present techniques for computing equivalent capacitance to be computationally infeasible.
Hence, what is needed is a method and an apparatus to quickly and accurately estimate the equivalent capacitances for a set of signal nets in the presence of fill nets.